Nonvolatile memory devices include a plurality of nonvolatile memory cells and peripheral circuits for driving the nonvolatile memory cells. The nonvolatile memory cells may be programmed or erased using a high voltage of about 10 to 20 V. Also, data stored in the nonvolatile memory cells may be read using a low voltage of about 5 V or lower. Thus, the peripheral circuits may include high-voltage MOS transistors used in the program and erase operations as well as low-voltage MOS transistors used in the read operation. In general, each of the nonvolatile memory cells adopts a stacked gate structure. The stacked gate structure includes a floating gate, an inter-gate dielectric layer and a control gate electrode, which are sequentially stacked.
As the nonvolatile memory devices become more highly integrated, the nonvolatile memory cells have been scaled down in size. Nevertheless, there may be a limitation in reducing the equivalent oxide thickness of the inter-gate dielectric layer. As a result, if the nonvolatile memory cells are shrunk in order to increase the integration density of the nonvolatile memory devices, the coupling ratio of the nonvolatile memory cells is decreased to make it difficult to lower the program and erase voltages. Therefore, it is difficult to scale down the high-voltage MOS transistors since the high-voltage MOS transistors should be designed to have a breakdown voltage higher than the program and erase voltages. The program and erase voltages may be directly related to the drain breakdown voltages of the high-voltage MOS transistors.
FIG. 1 is a cross-sectional view illustrating a conventional high-voltage MOS transistor.
Referring to FIG. 1, an isolation layer 3 is provided in a predetermined region of a semiconductor substrate 1 to define a high-voltage active region 3a. A source region 12s and a drain region 12d are provided in both ends of the high-voltage active region 3 a, respectively. A high-voltage gate electrode 7 is disposed over the substrate 1 between the source and drain regions 12s and 12d, and a high-voltage gate insulating layer 5 is interposed between the high-voltage gate electrode 7 and the substrate 1. The drain region 12d may include a heavily doped drain region 11d spaced apart from the high-voltage gate electrode 7 and a drain extension 9d extending from the heavily doped drain region 11d to be adjacent to the high-voltage gate electrode 7. Similarly, the source region 12s may include a heavily doped source region 11s spaced apart from the high-voltage gate electrode 7 and a source extension 9s extending from the heavily doped source region 11s to be adjacent to the high-voltage gate electrode 7. The source and drain extensions 9s and 9d have an impurity concentration lower than that of the heavily doped source and drain regions 11s and 11d. 
When the high-voltage MOS transistor shown in FIG. 1 is an NMOS transistor, the high-voltage MOS transistor may be turned off by grounding the high-voltage gate electrode 7, the source region 12s and the semiconductor substrate 1 and applying a positive drain voltage VD to the drain region 12d. In this case, if the drain voltage VD increases, the drain extension 9d may be depleted. In addition, if the drain voltage VD further increases, a gate electric field Eg between the high-voltage gate electrode 7 and the heavily doped drain region 11d increases. Increase of the gate electric field Eg may causes drain leakage current IL corresponding to a band-to-band tunneling current that flows through a junction region between the heavily doped drain region 11d and the substrate 1. The drain leakage current IL is referred to as a gate induced drain leakage (GIDL) current. The GIDL current should be suppressed in order to improve the drain breakdown voltage of the high-voltage MOS transistor.
The GIDL current may be generated due to a high electric field between the high-voltage gate electrode 7 and the heavily doped drain region 11d. Accordingly, there is a need to increase a distance D between the high-voltage gate electrode 7 and the heavily doped drain region 11d in order to increase the drain breakdown voltage of the high-voltage MOS transistor. However, if the distance D between the high-voltage gate electrode 7 and the heavily doped drain region 11d increases, the area occupied by the high-voltage MOS transistor may also increase to degrade the integration density of a semiconductor device.
A MOS transistor for suppressing the GIDL current is disclosed in Korean Patent No. 10-0436287 to Suh, entitled “Transistor of Semiconductor Device and Method of Fabricating the Same”. According to Suh, first and second auxiliary electrodes are provided at both sides of a gate electrode of a transistor, respectively. The first auxiliary electrode overlaps a source region, and the second auxiliary electrode overlaps a drain region. The gate electrode and the second auxiliary electrode are connected to first and second voltage supply sources, respectively. When a negative voltage is applied to the gate electrode in order to turn off the transistor, a voltage of 0 V is applied to the second auxiliary electrode so that a GIDL current flowing through a junction of the drain region can be suppressed.